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Language: English | Size: 1.49 GB | Duration: 4h 44m
VLSI - Building a chip is like building a city!!
What you'll learn
Understand Industrial Physical Design Flow
Modify and Develop own Flow as per Specifications
Requirements
Basic Digital Design
Description
The course is designed in the form of micro-videos, which delivers content in the form of Info-Graphics. It is designed for self-learning and will help to polish the Industrial skills in VLSI World. This course will cover end-to-end description from basic Device Physics to Chip Design.
We have contributed anonymously to this website, just to share the part of knowledge learned all these years, with the students keen to learn the basic concepts of the Chip Design. And also shared our industrial experience to give the technological exposure of current development in chip world...
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We upload these learning materials for the people from all over the world, who have the talent and motivation to sharpen their skills/ knowledge but do not have the financial support to afford the materials. If you like this content and if you are truly in a position that you can actually buy the materials, then Please, we repeat, Please, Support Authors. They Deserve it! Because always remember, without "Them", you and we won't be here having this conversation. Think about it! Peace...
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FILE LIST
Filename
Size
~Get Your Files Here !/01 - Physical Design Flow Overview/001 Floor-Planning Steps.mp4
11.9 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/001 Floor-Planning Steps_en.vtt
14.9 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization.mp4
15.2 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/002 Netlist Binding And Placement Optimization_en.vtt
13.1 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/003 Placement Timing And Clock Tree Synthesis.mp4
18.3 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/003 Placement Timing And Clock Tree Synthesis_en.vtt
12.7 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/004 Clock Net Shielding.mp4
14.7 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/004 Clock Net Shielding_en.vtt
13.6 KB
~Get Your Files Here !/01 - Physical Design Flow Overview/005 Route - DRC Clean - Parasitics Extraction - Final STA.mp4
22.2 MB
~Get Your Files Here !/01 - Physical Design Flow Overview/005 Route - DRC Clean - Parasitics Extraction - Final STA_en.vtt
12.7 KB
~Get Your Files Here !/02 - Floorplanning/001 Utilization Factor And Aspect Ratio.mp4
8.9 MB
~Get Your Files Here !/02 - Floorplanning/001 Utilization Factor And Aspect Ratio_en.vtt
12.5 KB
~Get Your Files Here !/02 - Floorplanning/002 Concept Of Pre-Placed Cells.mp4
8.8 MB
~Get Your Files Here !/02 - Floorplanning/002 Concept Of Pre-Placed Cells_en.vtt
13.3 KB
~Get Your Files Here !/02 - Floorplanning/003 De-coupling Capacitors.mp4
11.4 MB
~Get Your Files Here !/02 - Floorplanning/003 De-coupling Capacitors_en.vtt
13.5 KB
~Get Your Files Here !/02 - Floorplanning/004 Power Planning.mp4
12.3 MB
~Get Your Files Here !/02 - Floorplanning/004 Power Planning_en.vtt
15 KB
~Get Your Files Here !/02 - Floorplanning/005 Pin Placement And Logical Cell Placement Blockage.mp4
46.2 MB
~Get Your Files Here !/02 - Floorplanning/005 Pin Placement And Logical Cell Placement Blockage_en.vtt
13.6 KB
~Get Your Files Here !/03 - Placement/001 Net-list Binding And Placement.mp4
46.3 MB
~Get Your Files Here !/03 - Placement/001 Net-list Binding And Placement_en.vtt
13.2 KB
~Get Your Files Here !/03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance.mp4
91.3 MB
~Get Your Files Here !/03 - Placement/002 Optimize Placement Using Estimated Wire Length And Capacitance_en.vtt
14.4 KB
~Get Your Files Here !/03 - Placement/003 Optimize Placement Conitnued.mp4
86.9 MB
~Get Your Files Here !/03 - Placement/003 Optimize Placement Conitnued_en.vtt
12.1 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time.mp4
31.5 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/001 Setup Timing Analysis And Introduction to Flip-Flop Setup Time_en.vtt
13.2 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/002 Introduction To Clock Jitter and Uncertainty.mp4
41 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/002 Introduction To Clock Jitter and Uncertainty_en.vtt
10.6 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/003 Setup Timing Analysis with Multiple Clocks.mp4
34.4 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/003 Setup Timing Analysis with Multiple Clocks_en.vtt
11.7 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/004 Multiple Clock Timing Analysis And Introduction To Data Slew Check.mp4
72.8 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/004 Multiple Clock Timing Analysis And Introduction To Data Slew Check_en.vtt
12.5 KB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/005 Data Slew Check.mp4
82.8 MB
~Get Your Files Here !/04 - Timing Analysis With Ideal Clocks/005 Data Slew Check_en.vtt
13 KB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/001 Clock Tree Routing And Buffering using H-Tree Algorithm.mp4
66.5 MB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/001 Clock Tree Routing And Buffering using H-Tree Algorithm_en.vtt
12.9 KB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/002 Crosstalk And Clock Net Shielding.mp4
59.2 MB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/002 Crosstalk And Clock Net Shielding_en.vtt
13 KB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/003 Static Timing Analysis With Real Clocks.mp4
47.7 MB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/003 Static Timing Analysis With Real Clocks_en.vtt
15.9 KB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/004 Hold Timing Analysis Concluded.mp4
74.5 MB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/004 Hold Timing Analysis Concluded_en.vtt
14.1 KB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/005 Multiple Clocks Setup Timing Analysis With Real Clocks.mp4
58 MB
~Get Your Files Here !/05 - Clock Tree Synthesis And Signal Integrity/005 Multiple Clocks Setup Timing Analysis With Real Clocks_en.vtt
11.4 KB
~Get Your Files Here !/06 - Routing And Design Rule Check (DRC)/001 Introduction to Maze Routing - Lee's Algorithm.mp4
88.2 MB
~Get Your Files Here !/06 - Routing And Design Rule Check (DRC)/001 Introduction to Maze Routing - Lee's Algorithm_en.vtt
12.4 KB
~Get Your Files Here !/06 - Routing And Design Rule Check (DRC)/002 Lee's Algorithm Conclusion.mp4
114.9 MB
~Get Your Files Here !/06 - Routing And Design Rule Check (DRC)/002 Lee's Algorithm Conclusion_en.vtt
14 KB
~Get Your Files Here !/06 - Routing And Design Rule Check (DRC)/003 Design Rule Check.mp4
99.5 MB
~Get Your Files Here !/06 - Routing And Design Rule Check (DRC)/003 Design Rule Check_en.vtt
13.7 KB
~Get Your Files Here !/07 - Parasitics Extraction/001 Introduction to IEEE 1481 - 1999 SPEF format.mp4
78.6 MB
~Get Your Files Here !/07 - Parasitics Extraction/001 Introduction to IEEE 1481 - 1999 SPEF format_en.vtt
12.5 KB
~Get Your Files Here !/07 - Parasitics Extraction/002 SPEF Representation of a NET.mp4
65.8 MB
~Get Your Files Here !/07 - Parasitics Extraction/002 SPEF Representation of a NET_en.vtt
11.3 KB
~Get Your Files Here !/07 - Parasitics Extraction/003 Distributed Resistance And Capacitance Representation in SPEF.mp4
79 MB
~Get Your Files Here !/07 - Parasitics Extraction/003 Distributed Resistance And Capacitance Representation in SPEF_en.vtt
14.2 KB
~Get Your Files Here !/07 - Parasitics Extraction/004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!.mp4
41.7 MB
~Get Your Files Here !/07 - Parasitics Extraction/004 SPEF Header Description, Physical Design Flow Conclusion and What Next !!_en.vtt
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